(a) Field of the Invention
The present invention relates to a liquid crystal display device and, more particularly, to a liquid crystal display device which is provided with a printed circuit board (PCB) module adapted for a wide screen and high resolution device.
(b) Description of the Related Art
Generally, a liquid crystal display device includes a liquid crystal display module with a liquid crystal panel where liquid crystal cells are arranged between two glass substrates in a matrix form, and a backlight unit installed at the rear of the liquid crystal panel, a PCB module installed at the rear of the backlight unit to drive the liquid crystal panel, and a case covering the liquid crystal display module and the PCB module to protect them. The PCB module is a driving circuit that receives picture data of red (R), green (G) and blue (B) and synchronization signals from outside, and processes them to generate picture signals, scanning signals and timing control signals. The PCB module transmits the generated signals to the liquid crystal panel such that the latter can display the desired images in a stable manner. Such a PCB module is provided with a plurality of PCBs, and flexible printed cables (FPCs) interconnecting the PCBs for signal transmission.
FIG. 1 is a block diagram illustrating the circuit structure of a liquid crystal display device according to a prior art. As shown in FIG. 1, the PCB module for a display device bearing relatively lower resolution of SVGA (600*800) includes a main PCB 10, a gate driver PCB 20, and a source driver PCB 30 or 40. The main PCB 10 receives picture data of R, G and B and synchronization signals from the outside, and processes them by way of a timing controller (T-con) such that they are adapted for the structure of a liquid crystal panel 50. The timing controller is a custom IC in the form of a flat pin grid array (FPGA).
Gate driver IC tape automated bonds (TABs) are attached to the gate driver PCB 20 to receive gate driver control signals 60 and 61 from the main PCB 10, and to supply scanning signals to the liquid crystal panel 50 based on the received control signals 60 and 61. Source driver IC TABs are attached to the source driver PCB 30 or 40 to receive source driver control signals 70 and 71 from the main PCB 10, and to supply picture signals to the liquid crystal panel 50 based on the received control signals 70 and 71.
The PCB module further includes an FPC for transmitting the gate driver control signals 60 and 61 from the main PCB 10 to the gate driver PCB 20, and an FPC for transmitting the source driver control signals 70 and 71 from the main PCB 10 to the source driver PCB 30 or 40. In case the main PCB 10 is separated into two or more portions, other FPCs may be provided to interconnect the separated portions of the main PCB 10.
As the liquid crystal display device has been developed to bear a wide screen and a high resolution of XGA (768*1024), SXGA (1024*1280), or UXGA (1200*1600), a dual bank type PCB module is mainly used for such a display device because of the narrow width of data lines placed at a bottom substrate of the liquid crystal panel 50 and the space for driver IC TABs. The dual bank type PCB also allows a partitioned driving that enables high speed data processing. In the dual bank type PCB module, two source driver PCBs are installed at the rear of the liquid crystal panel 50 to supply picture signals from the top and the bottom.
FIGS. 2 and 3 illustrate the structure of a dual bank type PCB module for a liquid crystal display device, respectively.
As shown in FIG. 2, source driver PCBs 110 and 120 are installed at the rear of a liquid crystal display module 100 such that they are connected to an I-shaped main PCB 140 via FPCs 150 and 170, respectively. A gate driver PCB 130 is connected to the main PCB 140 via an FPC 160 side by side. The main PCB 140 has a timing controller to generate various kinds of data and control signals, and supply them to the source driver PCBs 110 and 120 and the gate driver PCB 130 via the FPCs 150, 160 and 170.
As shown in FIG. 3, source driver PCBs 210 and 220 are installed at the rear of a liquid crystal display module 200 such that they are connected to three main PCBs 240, 241 and 242 via FPCs 250 and 280, respectively. A gate driver PCB 230 is connected to the main PCB 240 via an FPC 290 side by side. The main PCBs 240, 241 and 242 are provided with a timing controller to generate various kinds of data signals and control signals, and supply them to the source driver PCBs 210 and 220 and the gate driver PCB 230 via the FPCs 250, 260, 270, 280 and 290.
However, in the usual dual bank type PCB module shown in FIG. 2, the transmission of the picture data is delayed at the right screen portion when viewed from the front side so that normal display cannot be made. In order to overcome such a problem, as shown in FIG. 3, it is proposed that three separate main PCBs 240, 241 and 242 should be introduced and interconnected via two FPCs 260 and 270. A space for mounting driver IC TABs, signal lines, resistors and condensers is provided at the source driver PCBs 210 and 220, and the main PCBs 240, 241 and 242 are designed in consideration of intersignal coupling, noise, and electromagnetic interference (EMI) such that the required signal transmission can be made within the range of tolerance. However, even in such a structure, signal delay or distortion tends to generate due to the delay factor intrinsic to resistance capacitance (RC) from interconnecting the PCBs by the FPCs 260 and 270. The RC may accrue to the combination resistance of the PCB connector and the FPC connector, and other parasitic capacitance. Consequently, the signals applied to the source driver PCBs 210 and 220 are not timing-controlled in a stable manner so that setting and holding of the picture data become to be inappropriate for displaying, resulting in serious display failure accompanied with screen noise and line defect.
Meanwhile, the usual liquid crystal display screen is formed in a rectangular shape where the ratio of the horizontal length to the vertical length is 4:3, or 16:9. However, in near future, it is expected that the display screen for medical equipment and radar where screen size and resolution become bigger and higher with a longer vertical length may be required in a square shape. Accordingly, the number of horizontal lines per frame increases in signal processing. Hence, one horizontal synchronization signal cycle becomes shorter to reduce the period of time for processing the picture data. This decreases timing margin. In this respect, it is required to develop a technique that processes the picture data within the range of signal delay and distortion tolerance, while preventing screen noise, coupling, and EMI.